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M8020A Keysight Bit Error Rate Tester
-BERT High-Performance BERTs
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M8020A Keysight Bit Error Rate Tester
C16: Data rate from 150 Mb/s to 16.2 Gb/s (option G16 or C16) for pattern generation and error detection / 0G3: Built in jitter injection / 0G4: Built in 8 tap de-emphasis / 0G5: Adjustable ISI offered for M8041A and M8051A / 0G7: Simultaneous common mode and differential mode level interference / M8020A-BU1: All M8020A-BU1 licenses have been pre-installed (except for a floating/networked license). All other system configurations require license installation as described in this step. / M9505A: Rack mount kit for AXIe 5-slot chassis / -U20 / M8070B: System software / M8070ADBV: 0NP floating/networked license / M9536A / -WE6 / M8041 A-UG2: high-performance BERT generator-analyzer-clock 8/16 Gb/s / N5990A-103: Test automation software for SATA receiver test / N5990A-303: SATA link training suite /
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J-BERT M8020A High-Performance BERT

The high-performance Keysight J-BERT M8020A enables fast, accurate receiver characterization of single- and multi-lane devices running up to 16 or 32 Gb/s.

With today’s highest level of integration, the M8020A streamlines your test setup. In addition, automated in situ calibrations of signal conditions ensures accurate and repeatable measurements. Through interactive link training, it can behave like the link partner of your device under test. The J-BERT M8020A will accelerate insight into your design.

Target Applications

The M8020A is designed for research and development engineers and test engineers who characterize and verify compliance of chips, devices, boards, and systems with serial I/O ports up to 16 Gb/s and 32 Gb/s. The M8020A can be used to test popular serial bus standards, such as PCI Express, USB, MIPI M-PHYTM, SATA/SAS, DisplayPort, SD UHS-II, Fibre Channel, memory buses, backplanes, repeaters, active optical cables, Thunderbolt, 10 GbE, 100 GbE (optical and electrical), SFP+, CFP2/4 transceivers, and CEI.

  • data rates up to 8.5/ 16 Gb/s for pattern generator and error detector
  • expandable to 32 Gb/s with M8062A, 32 Gb/s BERT front-end
  • integrated and calibrated jitter injection: RJ, PJ1, PJ2, SJ, BUJ, sinusoidal interference (common-mode and differential-mode), SSC (triangular and arbitrary, residual)
  • 8-tap de-emphasis (positive and negative) up to 20 dB
  • integrated and adjustable ISI for loss emulation
  • interactive link training for SAS-3, USB 3.0/3.1 and PCI Express supporting 8 GT/s and 16 GT/s
  • interactive TxEQ training for IEEE 10GBASE-KR, 25GBASE-KR, and 100GBASE-KR4
  • built-in clock data recovery and equalization
  • system integration with M8070A software for M8000 BER series
  • seamless operation with BERT/scope and arbitrary waveform generators

 

Option
Option Description
-U20
-WE6
0G3 Built in jitter injection
0G4 Built in 8 tap de-emphasis
0G5 Adjustable ISI offered for M8041A and M8051A
0G7 Simultaneous common mode and differential mode level interference
0S2
C16 Data rate from 150 Mb/s to 16.2 Gb/s (option G16 or C16) for pattern generation and error detection
G32 32Gb/s Pattern Generator Front End
M8020A-BU1 All M8020A-BU1 licenses have been pre-installed (except for a floating/networked license). All other system configurations require license installation as described in this step.
M8041 A-UG2 high-performance BERT generator-analyzer-clock 8/16 Gb/s
M8070ADBV 0NP floating/networked license
M8070B System software
M9505A Rack mount kit for AXIe 5-slot chassis
M9536A
N5990A-103 Test automation software for SATA receiver test
N5990A-303 SATA link training suite
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