Detail
J-BERT high-performance serial BERT up to 7 Gb/s and 12.5 Gb/s with complete jitter tolerance
Option
| Option | Description |
|---|---|
| 002 | Second output channel/ PRBS and pattern on aux data output |
| 003 | Half-rate clock with variable duty cycle |
| A01 | Bit recovery mode |
| A02 | SER/FER analysis |
| C07 | |
| C13 | 150Mb/s to 12.5Gb |
| CTR | |
| J10 | RJ, sRJ, PJ1, PJ2, SJ, BUJ injection |
| J11 | SSC, rSSC generation |
| J12 | Automated jitter tolerance compliance |
| J20 | Interference channel (includes short cable kit N4915A-008) |
| N4880A | Reference Clock Multiplier |
| N4910A | 2.4mm matched pair cable |
| N4915A-010 | Matched cable pair for connecting N4903B with N4916B (1X2.4mm to SMA for data, 1XSMA to SMA for clock, 167ps longer |
| N4916B-STD | 4-tap de-emphasis signal converter with optional clock multiplier |
| U13 | Data rate To 12.5Gb/s (N4903B-C13/ N4903B-G13) from 7Gb/s |
| UAB | Upgrade from N4903A version (factory, S/N will change) |
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